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HT -- 6560A VL_BUS IDE CONTROLLER
A. General Description --
JAN.04.1994 PAGE: 1
HT-6560A is a VL_Bus IDE controller which provides a control logic and data path between 486, 386 VL_Bus and IDE drives. The HT-6560A is fully compatible with the ANSI ATA revision 3.0 specification for IDE hard disk operation and VESA VL_Bus revision 1.0 specification for local bus PC drives. The HT-6560A is a high performance and fully design for IDE application. At the host CPU interface, HT-6560A provides a posted write and pre-fetched read fully 32 bits data path. It can operate up to 50 MHz and zero wait-state cycle. Double word read and write operations are provided. It also allows concurrent IDE and CPU memory operations to maximize system performance. Flexible IDE drive interface timing selection. Power on reset latch the adequate IDE active and recovery time into config register. HT-6560A also allows you detect IDE performance and change the config register by software program or BIOS.
B. Features --
* * * * * * * * * *
VESA VL_Bus rev 1.0 compatible. Connects directly to VL_Bus and IDE interface no extra TTL needed. Supports 16 bits and 32 bits data transfer. Zero wait_state 50MHz operation. Support read pre-fetch, posted write and I/O channel ready function. Support various type of ANSI ATA compatible IDE drives. Program mable command active and recovery time. Support primary and secondary I/O port selection. 100-pin PQFP package. BIOS and software driver supported.
HT -- 6560A VL_BUS IDE CONTROLLER
C. Block Diagram --
JAN.04.1994 PAGE: 2
D. Pin Assignment --
HT -- 6560A VL_BUS IDE CONTROLLER
E. Pin Description --
Pin No. 1 Pin Name HCI I/O I Description
JAN.04.1994 PAGE: 3
Command recovery time counter bit 1. This signal is negated to extend the host transfer cycle of any host command or data register access when the drive is not ready to respond to a data transfer request. When IORDY is not negated, IOCHRDY is in a high impedance state. +5V POWER. GROUND. Drive I/O read is an active low output which enables data to be read from the drive. The duration and repetition rate of DIORN cycles is determined by the type of IDE drive and programmed by HT-6560A. Drive I/O write is an active enables data to be written duration and repetition rate is determined by the type programmed by HT-6560A. low output which to the drive. The of DIOWN cycles of IDE drive and
2
IORDY
I
3,28,53,78 4,15,29,40,54, 65,79,90
VDD VSS
-- --
5
DIORN
O
6
DIOWN
O
7
RDYRTNN
I
Ready return is an active low signal which indicates the end of the current host CUP transfer. Address strobe is an active low input signal which indicates that there is a valid address and command on the bus. Write (active high) or read (active low) is an input which distinguishes between write and read cycles. Memory (active high) or I/O (active low) is an input which distinguished between momory and I/O cycles. Data (active high) or control (active low) is an input which is used to distinguish between I/O and interrupt or halt cycles.
8
ADSN
I
9
WRN
I
10
MION
I
11
DCN
I
HT -- 6560A VL_BUS IDE CONTROLLER
JAN.04.1994 PAGE: 4
Pin No. 12
Pin Name S0
I/O I
Description Primary or secondary I/O port selection input. Level high for primary, level low for secondary I/O port. Disk change is an input which comes from floopy diskette drive connector pin 34. Drive chip select 1 is normal an active low output which used to select the command block registers in the drive. This pin is an input which is com mand active time counter bit 3 during power on reset and sampled on the rising edge of RSTN. Drive chip select 3 is normal an active low output which used to select the control block registers in the drive. This pin is an input which is command recovery time counter bit 2 during power on reset and sampled on the rising edge of RSTN. Drive address, bit 2, is normally output to the IDE connector for register selection in the drive. This pin is an input which is com mand active time counter bit 2 during power on re set and sam pled on the rising edge of RSTN. Drive address, bit 1, is normally output to the IDE connector for register selection in the drive. This pin is an input which is com mand active time counter bit 1 during power on re set and sam pled on the rising edge of RSTN. Drive address, bit 0, is normally output to the IDE connector for register selection in the drive. This pin is an input which is com mand active time counter bit 0 during power on re set and sam pled on the rising edge of RSTN. These are the host address bits 2 through bits 15 from the host address bus.
13
DSKCHGN
I
14
CS1FXN
I/O
16
CS3FXN
I/O
17
DA2
I/O
18
DA1
I/O
19
DA0
I/O
20~27,30~35
LA2~LA15
I
HT -- 6560A VL_BUS IDE CONTROLLER
JAN.04.1994 PAGE: 5
Pin No. 36
Pin Name LDEVN
I/O O
Description Local device is an active low output which indicates that the current host CPU com mand cycle is a valid HT-6560A address.
37
LRDYN
Local ready is an active low output which indicates that the current host CPU transfer Tri-O h a s co m p le te d . A s th e c u rr e n t cycle is completed, the LRDYN will immediately pull low and remain active for one T-state. Host data is the 32 bits bi-directional data bus which connects to the host CPU LD[7:0] define the lowest data byte while LD[31:24] define the most significant data byte. The active bytes on a CPU transfer are specified b y th e B E N [3 :0 ] s ig n a ls . T h e L D bu s is n o r m a lly in h ig h im p e d a nce state an d is driven only after T2 state of HT-6560A read cycles. VL_Bus clock. Drive data bus, bits 15 through 0, are the 16 bits bi-directional data bus which connects to the IDE drive. DD[7:0] define the lowest data byte while DD[15:8] define the most significant data byte. System reset is an active low input. Byte enable bits 0 through 3 from the host CPU address bus. These inputs are active low and specify which bytes will be valid for host read/write data transfers. ID E enable is an active high input w hich enable the HT-6560A for drive operation. Low input which disables HT-6560A. Command recovery time counter bit 0.
38,39,46,48~52, 58~60,62~64, LD31~LD0 71~76,83,85~89 ,91,93~96,98
I/O
41
CLK
I
42~44,47,55,56, 61,69,70,77,81, DD15~DD0 82,84,92,97,99 45 RSTN
I/O
I
57,66~68
BEN3~0
I
80 100
IDEEN HC0
I I
HT -- 6560A VL_BUS IDE CONTROLLER
F. Absolute Maximum Ratings --
Parameter Supply Voltage Input/Output Voltage Storage Temperature Temperature Under Bias Plastic Plastic Symbol V DD V I ,V O T STG T BIAS Minimum -0.5 V SS -0.5 -40 -40 Maximum 6 V DD +0.5 125 85
JAN.04.1994 PAGE: 6
Unit V V
C C
Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of the data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V SS =0V.
G. Recommended Operating Conditions --
Parameter Supply Voltage Input High Voltage for Normal Input Input Low Voltage for Normal Input Operating Temperature Symbol V DD V IH V IL TA Min. 4.75 2.2 -- 0C Typ. 5 -- -- 25C Max. 5.25 -- 0.8 70C Unit V V V
C
H. DC Characteristics --
Symbol I DDS V OH1 Parameter Power Supply Current O u tp ut H igh Volta ge for N o rm a l O u tpu t (L D [3:0], LRDYN, LDEVN) Output High Voltage for Driver O u tp u t ( D D [1 5:8], D A [0:2], C S 1 F X N , C S 3F X N , D IO R N , DIOWN) Output High Voltage for Driver Output (DD[0:7]) Condition Steady state. I OH =-2mA Min. -- 4 Typ. -- -- Max. 0.2 V DD Unit mA V
V OH2
I OH =-4mA
4
--
V DD
V
V OH3
I OH =-0.8mA
4
--
V DD
V
HT -- 6560A VL_BUS IDE CONTROLLER
JAN.04.1994 PAGE: 7
Symbol V OL1
Parameter
Condition
Min. V SS
Typ. --
Max. 0.4
Unit V
O u tp u t Low Vo lta g e for I OL =3.2mA or N o rm a l O u tp u t ( LD [3 1:0], 8mA LRDYN, LDEVN) Output Low Voltage for Driver O u tp u t ( D D [1 5:8], D A [0:2], C S 1 F X N , C S 3F X N , D IO R N , DIOWN) Output Low Voltage for Driver Output (DD[0:7]) Input High Voltage
V OL2
I OL =12mA
V SS
--
0.4
V
V OL3 V IH
I OL =24mA Normal Schmitt Trigger
V SS 2.2 2.4 V SS V SS -10 -10 25 5
-- -- -- -- -- -- --
0.5 V DD V DD 0.8 0.6 10 10
V V V V V
A A
V IL I LI I LZ RP RN
Input Low Voltage Input Leakage Current Input Leakage Current Input Pull-Up Resistor Input Pull-Down Resistor
Normal Schmitt Trigger V I =0-V DD Tri-state V I =0-V DD V IH =V DD V IL =V SS
50
100
K
I. Capacitance -- (Ta=25C, VDD=VI=0V, f=1MHz)
Symbol C IN C OUT C OUT C I/O C I/O Parameter Input Pin Capacitance Output Pin Capacitance (I OL =3.2/8/12mA) Output Pin Capacitance (I OL =24mA) I/O Pin Capacitance (IOL=3.2/8/12mA) I/O Pin Capacitance (IOL=24mA) Test Condition V DD Condition 16 16 18 16 18
PF PF
Min.
Typ.
Max.
Unit
PF
PF
PF
HT -- 6560A VL_BUS IDE CONTROLLER
J. Functional Description --
JAN.04.1994 PAGE: 8
The HT-6560A contains five major blocks as shown in fig.1. They are state control unit, address decoder, read ahead buffer, posted write buffer, config register. The state control unit contains a state machine which controls all of the read/write timing and data swapping to IDE drives. The address decoder connects to VL_Bus directly, decodes valid address of the HT-6560A config register and IDE drive registers. Read ahead buffer and posted write buffer which can accelerate the data read/write speed. The config register let user can set the command active and recovery time to optimize the IDE performance. In addition to, you can detect or set primary or secordary IDE port through the config register.
1. Restet Initialization Siganl Name CS1FXN CS3FXN LDEVN DIOWN DIORN LRDYN DA[2:0] LD[31:0] DD[15:0] Signal State During Reset Hight-Impedance Hight-Impedance High-Impedance 1 1 High-Impedance High-Impedance High-Impedance High-Impedance
HT -- 6560A VL_BUS IDE CONTROLLER
JAN.04.1994 PAGE: 9
2. Host Interface a. CPU Cycle Definition: MION 0 0 0 0 1 1 1 1 DCN 1 1 0 0 0 0 1 1 WRN 0 1 0 1 0 1 0 1 Address Space 1F0h-1F7h and 3F6h for primary drive. 170h-177h and 376h for secondary drive. 1F0h-1F7h and 3F6h for primary drive. 170h-177h and 376h for secondary drive. Don't care. Don't care. Don't care. Don't care. Don't care. Don't care. IDE Cycle DIORN CYCLE DIOWN CYCLE NOP NOP NOP NOP NOP NOP
b. HT-6560A Write Data Operation: CPU Write Byte Enable BEN3 0 0 1 1 1 1 BEN2 0 1 0 1 1 1 BEN1 0 1 1 0 0 1 BEN0 0 1 1 0 1 0 HT-6560A Input Data LD[31:24] LD[23:16] LD[15:8] valid valid X X X X valid X valid X X X valid X X valid valid X LD[7:0] valid X X valid X vaild
HT -- 6560A VL_BUS IDE CONTROLLER
JAN.04.1994 PAGE: 10
c. HT-6560A Read Data Operation CPU Write Byte Enable BEN3 0 0 1 1 1 1 BEN2 0 1 0 1 1 1 BEN1 0 1 1 0 0 1 BEN0 0 1 1 0 1 0 LD[31:24] valid valid same as LD[23:16] HT-6560A Output Data LD[23:16] valid same as LD[31:24] valid LD[15:8] valid same as LD[31:24] same as LD[23:16] LD[7:0] valid same as LD[31:24] same as LD[23:16]
same as LD[15:0] same as LD[15:8] same as LD[7:0] same as LD[15:8] same as LD[7:0] valid
valid same as LD[15:8] valid
same as LD[7:0]
3. IDE Interface a. DA[2:0] Generation: LA2 0 0 0 0 1 1 1 1 BEN[3:0] XX00 XX01 X011 0111 XXX0 XX01 X011 0111 DA[2:0] 000 001 010 011 100 101 110 111
b. Drive Select Signal Operation: Signal Name CS1FXN CS3FXN Address Range 1F0h-1F7h for primary drive. 170h-177h for secondary drive. 3F6h-3F7h for primary drive. 376h-377h for secondary drive.
HT -- 6560A VL_BUS IDE CONTROLLER
K. HT-6560A Register Setting --
1. Active Time and Recovery Time Setting
JAN.04.1994 PAGE: 11
Suggest active time is 2~15 cycles which depend on IDE drive type and system speed. You can set this register by hardware or software setting. a. Hardware Setting: During power on reset, this register can be latched from following pins. Active Time: CS1FXN 0 0 0 DA2 0 0 1 DA1 1 1 0
DA0 0 1 0
Cycles 2 3 4
1
1
1
1
15
Recovery Time: CS3FXN 0 0 HC1 0 0
HC0 0 1
Cycles 8 9
1
1
1
15
b. Software Setting: After power on reset, you still can program the config register by following procedures:
* *
Read I/O port 3E6 four times to turn on config mode. Write 8 bits data to I/O port 1F6 (or 176)
HT -- 6560A VL_BUS IDE CONTROLLER
JAN.04.1994 PAGE: 12
Recovery Time: Data bit7 0 0
bit6 1 1
bit5 0 0
bit4 0 1
Cycles 4 5
1 0 0
1 0 0
1 0 0
1 0 1
15 16 17
Active Time: Data bit3 0 0
bit2 0 0
bit1 1 1
bit0 0 1
Cycles 2 3
1
1
1
1
15
*
Read I/O port 1F7 (or 177) one time to clear config mode.
2. Primary and Secondary I/O Port Setting a. Hardware Setting: During power on reset, this register can be latched from the S0 pin. S0 1 0 I/O Port 1F0~7, 3F6~7, (primary) 170~7, 376~7, (secondary)
HT -- 6560A VL_BUS IDE CONTROLLER
JAN.04.1994 PAGE: 13
b. Software Setting: After power on reset, you still can program the I/O port register by writing data to port 3E6. bit 0 1 0 I/O Port 1F0~7, 3F6~7, 3E6 (primary) 170~7, 376~7, 3E6 (secondary)
This bit also can be read in data bit 0 by reading port 3E6.
3. Register 3E6: bit 0: Primary and secondary I/O port setting. 1: Primary. 0: Secondary. bit 1: Define pre-fetched data read function, normally no pre-fetched data read function. 1: No pre-fetch function. 0: Pre-fetch. bit 2: If system is multi-master, then set it 0, normally 1 (not multi-master system). bit 3: Define address setup time, normally 1. 1:3 cycle time 0:2 cycle time
HT -- 6560A VL_BUS IDE CONTROLLER
L. Package Information --
JAN.04.1994 PAGE: 14
LD[0..31] VCC HDLDLLLLDL CDDDDDDDDD 0104000030 50 1234 5 LLLLLDLDD DDDDDDDDD 000012111 67890 143 0.1uf HT-6560A LD01 LD03 HC1 IORDY IDEEN VCC 19999999999888888888 09876543210987654321 0
VCC
LD00 LD02 LD04 LD06 LD08 LD05 LD07 LD09 LD11 LD13 LD15 C37 100Pf LD17 LD19 LD21 LD23 LD25 S0 DSKCHGZ DIORN DIOWN RDYRTN ADSN WRN MION DCN S0 DSKCHGZ CS1FXN DD1 LD12 LD13 LD14 LD15 LD16 LD17 DD0 DD12 BEN2 BEN1 BEN0
LD10 LD12
LD14 LD16 LD18 LD20
M. Application Circuit --
LD22 LD24 LD26 LD28 LD30
HT-6560A
LD27 LD29 LD31
LA[2..15] VCC LA14 LA12 LA10 LA08 LA10 LA06 LA04 1K BEN0 BEN1 BEN2 LA[2..15] BEN3 ADSN LLLLLLLLL AAAAADRDD 11111ED33 12345VY10 NN LDDDRLDLLL CDDDEDDDDD L589S26222 K E9 876 T N 33333333344444444445 12345678901234567890
CS3FXN DA2 DA1 DA0 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LD18 LD19 LD20 DD7 LD21 LD22 LD23 BEN3 DD11 DD10 LD24 LD25
VCC
LA15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LA13 LA11 LA09 LA07 LA05
HDLDLLLLDLVLLLLLDLDD C D D D D D D D D D S D D D D D D D D D IDEEN HC1 VSS IORDY 0 1 0 4 1 2 3 4 3 5 S 6 7 8 9 1 2 1 1 1 0 143 5 VDD VDD VSS DD1 DIORN LD12 DIOWN LD13 RDYRTNN LD14 ADSN LD15 WRN LD16 LD17 MION DCN DD0 S0 DD12 DSKCHGN BEN2 CS1FXN BEN1 VSS BEN0 VSS CS3FXN DA2 LD18 DA1 LD19 DA0 LD20 LA2 DD7 LA3 LD21 LA4 LD22 LA5 LD23 LA6 BEN3 LA7 DD11 LA8 DD10 LA9 VSS LL VDD VDD LLLLLDRLL RL LLL VSS LD24 AAAAAEDDDVCDDDSDDDDD LA10 LD25 11111VY33SLDDDT2D222 12345NN10SK589N96876
LA03 LA02
RESETN
RESETN DCN MION WRN
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 DAT01 DAT03 GND DAT05 DAT07 DAT09 DAT11 DAT13 DAT15 GND DAT17 VDC DAT19 DAT21 DAT23 DAT25 GND DAT27 DAT29 DAT31 ADR30 ADR28 ADR26 GND ADR24 ADR22 VDC AD20 ADR18 ADR16 ADR14 ADR12 ADR10 ADR08 GND ADR06 ADR04 WBACK# BE0# VDC BE1# BE2# GND BE3# ADS#
S3 DAT00 DAT02 DAT04 DAT06 DAT08 GND DAT10 DAT12 VDC DAT14 DAT16 DAT18 DAT20 GND DAT22 DAT24 DAT26 DAT28 DAT30 VDC ADR31 GND ADR29 ADR27 ADR25 ADR23 ADR21 ADR19 GND ADR17 ADR15 VDC ADR13 ADR11 ADR09 ADR07 ADR05 GND ADR03 ADR02 N/C RESET# D/C# M/IO# W/R# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
RDYRTN
HT -- 6560A
LCLK
106 107 108 109 110 111 112 113 114 115 116 LRDY# RDYRTN# LDEV# GND LREQ# IRQ9 GND BRDY# LGNT# BLAST# VDC ID0 ID2 ID1 ID3 GND ID4 LCLK LKEN# VDC LEADS# LBS16# VL-BUS CON
48 49 50 51 52 53 54 55 56 57 58 DD[0..15] HDD RESETN
VL_BUS IDE CONTROLLER
VCC VCC (ACTIVE TIME SETTING) CS1FXN 20K HC1 DA2 20K HC0 20K S0 4.7K 20K 1 2 3 4.7K 1 2 3 4.7K DA0 330 DA1 HDD LED VCC 12 123 4.7K HIRQ 1 2 3 4.7K CS3FXN 4.7K
VCC
RESETN DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
10K
IDEEN
1 2 3
20K
123
DIOWN DIORN IORDY HIRQ DA1 DA0 CS1FXN
20K
1 2 3 4.7K
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DA2 CS3FXN
PAGE:
20K
1 2 3 4.7K
JAN.04.1994
20K
123
15

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